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| IRF640, RF1S640, RF1S640SM Data Sheet January 2002 18A, 200V, 0.180 Ohm, N-Channel Power MOSFETs These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17422. Features * 18A, 200V * rDS(ON) = 0.180 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speed * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER IRF640 RF1S640 RF1S640SM PACKAGE TO-220AB TO-262AA TO-263AB BRAND IRF640 RF1S640 RF1S640 Symbol D G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in the tape and reel, i.e., RF1S640SM9A. S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) JEDEC TO-263AB GATE SOURCE DRAIN (FLANGE) JEDEC TO-262AA SOURCE DRAIN GATE DRAIN (FLANGE) (c)2001 Fairchild Semiconductor Corporation IRF640, RF1S640, RF1S640SM Rev. B IRF640, RF1S640, RF1S640SM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRF640, RF1S640, RF1S640SM 200 200 18 11 72 20 125 1.0 580 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC oC oC Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current On-State Drain Current (Note 1) Gate to Source Leakage Current TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured From the Contact Screw on Tab to Center of Die Measured From the Drain Lead, 6mm (0.25in) From Package to Center of Die Modified MOSFET Symbol Showing the Internal Devices Inductances D LD TEST CONDITIONS ID = 250A, VGS = 0V, (Figure 10) VGS = VDS , ID = 250A VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 125oC VDS > ID(ON) x rDS(ON)MAX , VGS = 10V (Figure 7) VGS = 20V ID = 10A, VGS = 10V (Figures 8, 9) VDS 10V, ID = 11A (Figure 12) VDD = 100V, ID 18A, RGS = 9.1, RL = 5.4, MOSFET Switching Times are Essentially Independent of Operating Temperature MIN 200 2 18 6.7 - TYP 0.14 10 13 50 46 35 43 8 22 1275 400 100 3.5 MAX 4 25 250 100 0.18 21 77 68 54 64 - UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH Drain to Source On Resistance (Note 1) Forward Transconductance (Note 1) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance VGS = 10V, ID 18A, VDS = 0.8 x Rated BVDSS (Figure 14) Gate Charge is Essentially Independent of Operating Temperature IG(REF) = 1.5mA VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 4.5 - nH Internal Source Inductance LS Measured From the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad G LS S 7.5 - nH Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA RJA Free Air Operation, IRF640 RF1S640SM Mounted on FR-4 Board with Minimum Mounting Pad - - 1 62 62 oC/W oC/W oC/W (c)2001 Fairchild Semiconductor Corporation IRF640, RF1S640, RF1S640SM Rev. B IRF640, RF1S640, RF1S640SM Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 2) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode G D MIN - TYP - MAX 18 72 UNITS A A S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge NOTES: VSD trr QRR TJ = 25oC, ISD = 18A, VGS = 0V, (Figure 13) TJ = 25oC, ISD = 18A, dISD/dt = 100A/s TJ = 25oC, ISD = 18A, dISD/dt = 100A/s 120 1.3 240 2.8 2.0 530 5.6 V ns C 2. Pulse Test: Pulse width 300s, duty cycle 2%. 3. Repetitive Rating: Pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 3.37mH, RG = 25, peak IAS = 18A. Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 Unless Otherwise Specified 20 0.8 0.6 0.4 0.2 0 ID, DRAIN CURRENT (A) 16 12 8 4 0 0 50 100 150 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 10 ZJC , TRANSIENT THERMAL IMPEDANCE (oC/W) 1 0.5 0.1 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE PDM 0.01 0.001 10-5 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 10-4 10-3 10-2 10-1 1 10 t1 t2 tP, RECTANGULAR PULSE DURATION (s) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE (c)2001 Fairchild Semiconductor Corporation IRF640, RF1S640, RF1S640SM Rev. B IRF640, RF1S640, RF1S640SM Typical Performance Curves 1000 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) TC = 25oC ID , DRAIN CURRENT (A) 100 10s 100s 10 1ms 10ms TC = 25oC TJ = MAX RATED SINGLE PULSE 1 1 10 100 DC ID , DRAIN CURRENT (A) Unless Otherwise Specified (Continued) 30 10V 8V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 7V 18 24 12 6V 6 5V 0 4V 0 12 24 36 48 60 1000 VDS , DRAIN TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS 30 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 8V VGS = 10V ID , DRAIN CURRENT (A) VGS = 7V 100 ID , DRAIN CURRENT (A) 24 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS 50V 10 18 VGS = 6V 25oC 150oC 1 12 6 VGS = 4V VGS = 5V 0 0 1.0 2.0 3.0 4.0 5.0 VDS , DRAIN TO SOURCE VOLTAGE (V) 0.1 0 2 4 6 8 VGS , GATE TO SOURCE VOLTAGE (V) 10 FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 1.5 rDS(ON) , DRAIN TO SOURCE ON RESISTANCE () 1.2 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 3.0 2.4 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 18A 0.9 1.8 0.6 1.2 0.3 VGS= 10V VGS = 20V 0.6 0 0 15 30 45 60 75 ID , DRAIN CURRENT (A) 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE (c)2001 Fairchild Semiconductor Corporation IRF640, RF1S640, RF1S640SM Rev. B IRF640, RF1S640, RF1S640SM Typical Performance Curves 1.25 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.15 C, CAPACITANCE (pF) 2400 Unless Otherwise Specified (Continued) 3000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 1.05 1800 CISS 1200 COSS 600 CRSS 0.95 0.85 0.75 -60 -40 -20 0 20 40 60 80 100 120 140 160 0 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 100 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 15 12 25oC 9 150oC 6 ISD , SOURCE TO DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1000 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 150oC gfs , TRANSCONDUCTANCE (S) 100 25oC 10 3 0 0 6 12 18 24 30 ID , DRAIN CURRENT (A) 1 0 0.4 0.8 1.2 1.6 VSD , SOURCE TO DRAIN VOLTAGE (V) 2.0 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS , GATE TO SOURCE VOLTAGE (V) ID = 28A 16 VDS = 40V VDS = 100V 12 VDS = 160V 8 4 0 0 15 30 45 60 75 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE (c)2001 Fairchild Semiconductor Corporation IRF640, RF1S640, RF1S640SM Rev. B IRF640, RF1S640, RF1S640SM Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT VDS (ISOLATED SUPPLY) FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDD SAME TYPE AS DUT 0.3F Qgs D VDS G DUT 0 IG(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR IG(REF) 0 Qg(TOT) Qgd VGS 12V BATTERY 0.2F 50k FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS (c)2001 Fairchild Semiconductor Corporation IRF640, RF1S640, RF1S640SM Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM DISCLAIMER FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R) SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R) VCXTM STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4 |
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